R8610 rdc ? risc dsp communication 32 bit risc micro controller specifications subject to change without notice, contact your sales representatives for the most update information. page 1 of 6 rev 1.1 sep. 05 2007 R8610 brief sheet 32 bit risc micro controller
R8610 rdc ? risc dsp communication 32 bit risc micro controller specifications subject to change without notice, contact your sales representatives for the most update information. page 2 of 6 rev 1.1 sep. 05 2007 1. features n embedded risc controller C full 32 bit risc architecture C supports diverse operation systems, including ms-windows, linux and most of the popular 32 bit rtos C 6-stage pipeline C operation frequency: 133 mhz C supports mmu function which includes 32 tlb entries n mac controller C supports two-port 10/100 fast ethernet mac C ieee 802.3u mii interface C ieee 802.3x flow control in full-duplex mode C descriptor architecture for packet tx/rx n interrupt controller C provides two 8259 compatible interrupt controllers which are cascaded internally C independent programmable level/edge-triggered interrupt channels C serial irq supported n dma controller C provides two 8237 dma compatible controllers which are cascaded internally C 4 channels for 8-bit dma transfer and 3 channels for 16 bit transfer n two usb 2.0 host port support C supports hs, fs and ls n fifo uart port C a high performance uart port with transmit and receive fifos C supports the programmable baud rate generator with the data rates from 50 to 115,200 bps C the character options are programmable for 1 start bit; 1, 1.5 or 2 stop bits; even, odd or no parity; 5~8 data bits n pci control interface C supports pci rev 2.1 specification C 32-bit bus interface C supports pci clock at 33 mhz C supports pci host C supports pci master/ slave C up to 133 mbytes / s ec. maximum bandwidth C supports up to 3 external master devices on pci C provides four pci interrupt channels n lpc ( low pin count ) bus interface C lpc revision 1.0 compliant C supports lpc/fwh ( firmware hub ) compliant interfaces C provides the interface to connect an lpc/fwh flash rom or super i/o chip C supports lpc dma C supports serial irq C supports 8/16/32-bit transfer size C supports bus master request in dma channel 4 n x-bus interface C provides the interface to boot rom bios & doc (disk on chip). C supports 8/16 bit data width C provides romcs_n for booting from x-bus flash rom C supports from 64k byte to max 16m byte rom space addressing C supports two independent and programmable css ( chip selects ) n sdram control interface C pc100/ pc133 compliant C supports 16-bit data bus width C supports speeds up to 133 mhz and above C supports maximum 128 mb memory space n on-chip l1 16kb cache C unified instructions and data cache C supports write through for cache write policy C snooping mechanism support for data coherence between main memory and cache C direct map n general programmable i / o C supports 58 programmable i/ o pins
R8610 rdc ? risc dsp communication 32 bit risc micro controlle r specifications subject to change without notice, contact your sales representatives for the most update information. page 3 of 6 rev 1.1 sep. 05 2007 C each gpio pin can be individually configured to be an input/output pin n counter / timers C 8254 compatible timers C provides three independent programmable timers / counters C supports a watchdog timer (wdt) C supports a speaker output n real time clock ( external ) C provides a direct interface to external rtc chips n operating voltage range C core voltage : 1 .8 v 5% C i / o voltage : 3.3 v 10% n operating temperature: 0 ~ +70 c n package type C 24mm x 24mm, 216- pin lqfp C 13mm x 13mm, 225 -pin lfbga n rohs compliant
R8610 rdc ? risc dsp communication 32-bit risc micro controller specifications subject to change without notice, contact your sales representatives for the most update information. page 4 of 6 rev 1.1 sep. 05 2007 2. block diagram sdram controller x-bus interace south bridge dma controller timer/ counter interrupt controller uart real time clock interface lpc interace north bridge rdc 32-bit cpu 16k-byte l1 cache pci bus sdram & x-bus interface pci bus interface lpc bus interface uart rtc interface mux usb2.0 host controller mac 1 mac 0 mii 0 mii 1 usb port 0 usb port 1
R8610 rdc ? risc dsp communication 32-bit risc micro controller specifications subject to change without notice, contact your sales representatives for the most update information. page 5 of 6 rev 1.1 sep. 05 2007 4. package information lqfp: 216 pins dimension in mm symbol min. nom. max. a -- -- 1.60 a 1 0.05 -- 0.15 a 2 1.35 1.40 1.45 b 0.13 0.18 0.23 d 25.85 26.00 26.15 d 1 23.90 24.00 24.10 e 25.85 26.00 26.15 e 1 23.90 24.00 24.10 e 0.40 bsc l 0.45 0.60 0.75 l 1 1.00 ref r 1 0.08 -- -- r 2 0.08 -- -- s 0.20 -- -- 0 3.5 7 1 0 -- -- 2 11 12 13 3 11 12 13
R8610 rdc ? risc dsp communication 32-bit risc micro controller specifications subject to change without notice, contact your sales representatives for the most update information. page 6 of 6 rev 1.1 sep. 05 2007 lfbga 225 balls
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